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A Hierarchical Timing Simulation Model

Lin, Tzu-Mu and Mead, Carver A. (1986) A Hierarchical Timing Simulation Model. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 5 (1). pp. 188-197. ISSN 0278-0070. http://resolver.caltech.edu/CaltechAUTHORS:20150123-155931107

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Abstract

A hierarchical timing simulation model has been developed to deal with VLSI designs at any level of representation. A set of physically based parameters are used to characterize the behavior and timing of a semantic design object (cell) independent of its composition environment. As cells are composed, the parameters of the composite cell can be determined from those of the component cells either analytically or by simulation. Based on this model, a behavior-level simulator has been developed and combined with other tools to form an integrated design system that fully supports the structured design methodology.


Item Type:Article
Related URLs:
URLURL TypeDescription
http://dx.doi.org/10.1109/TCAD.1986.1270186DOIArticle
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=1270186PublisherArticle
Additional Information:© 1986 IEEE. Manuscript received October 8. 1984. This work was supported by the System Development Foundation.
Funders:
Funding AgencyGrant Number
System Development FoundationUNSPECIFIED
Record Number:CaltechAUTHORS:20150123-155931107
Persistent URL:http://resolver.caltech.edu/CaltechAUTHORS:20150123-155931107
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:54038
Collection:CaltechAUTHORS
Deposited By: Kristin Buxton
Deposited On:24 Jan 2015 00:39
Last Modified:24 Jan 2015 00:39

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