Hoeneisen, B. and Mead, C. A. (1972) Fundamental limitations in microelectronics — I. MOS technology. Solid-State Electronics, 15 (7). pp. 819-829. ISSN 0038-1101. http://resolver.caltech.edu/CaltechAUTHORS:20150212-160423500
Full text is not posted in this repository. Consult Related URLs below.
Use this Persistent URL to link to this item: http://resolver.caltech.edu/CaltechAUTHORS:20150212-160423500
The physical phenomena which will ultimately limit MOS circuit miniaturization are considered. It is found that the minimum MOS transistor size is determined by gate oxide breakdown and drain-source punch-through. Other factors which limit device size are drain-substrate breakdown, drain ‘corner’ breakdown and substrate doping fluctuations. However these limitations are less severe than the oxide breakdown limitation mentioned above. Power dissipation and metal migration limit the frequency and/or packing density of fully dynamic and of complementary MOS circuits. In static non-complementary circuits, power dissipation is the principal limitation of the number of circuit functions per chip. The channel length of a minimum size MOS transistor is a factor of 10 smaller than that of the smallest present day devices. The tolerances required to manufacture such a transistor are compatible with electron beam masking techniques. It is thus possible to envision fully dynamic silicon chips with up to 10^7–10^8 MOS transistors per cm^2.
|Additional Information:||© 1971 Pergamon Press. Received 11 August 1971; in revised form 8 November 1971. This work was supported in part by the Office of Naval Research and the General Electric Co.|
|Usage Policy:||No commercial reproduction, distribution, display or performance rights in this work are provided.|
|Deposited By:||Kristin Buxton|
|Deposited On:||13 Feb 2015 03:41|
|Last Modified:||13 Feb 2015 03:41|
Repository Staff Only: item control page