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Signal Delay in General RC Networks with Application to Timing Simulation of Digital Integrated Circuits

Lin, Tzu-Mu and Mead, Carver A. (1984) Signal Delay in General RC Networks with Application to Timing Simulation of Digital Integrated Circuits. In: Proceedings, Conference on Advanced Research in VLSI : January 23-25, 1984, Massachusetts Institute of Technology, Cambridge, Massachusetts. Artech House , Dedham, MA, pp. 93-99. ISBN 089006136X . http://resolver.caltech.edu/CaltechAUTHORS:20150217-161323301

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Abstract

Modeling digital MOS circuits by RC networks has become a well accepted practice for estimating delays. In 1981, Penfield and Rubinstein proposed a method to bound the waveforms of nodes in an RC tree network. In this paper, a single value of delay is derived for any node in a general RC network. The effects of parallel connections and stored charges are properly taken into consideration. The algorithms can be used either as a stand-alone simulator, or as a front end for producing initial waveforms for waveform-relaxation based circuit simulators. An experimental simulator called SDS (Signal Delay Simulator) has been developed. For all the examples tested so far, this simulator runs two to three orders of magnitude faster than SPICE, and detects all transitions and glitches at approximately the correct time.


Item Type:Book Section
Additional Information:© 1984 Artech House. This research is sponsored by the System Development Foundation.
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System Development FoundationUNSPECIFIED
Record Number:CaltechAUTHORS:20150217-161323301
Persistent URL:http://resolver.caltech.edu/CaltechAUTHORS:20150217-161323301
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:54897
Collection:CaltechAUTHORS
Deposited By: Kristin Buxton
Deposited On:18 Feb 2015 02:55
Last Modified:18 Feb 2015 02:55

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