Pedroni, V. A. and Yariv, A. (1996) Single-clock-cycle two-dimensional median filter. Electronics Letters, 32 (5). pp. 440-441. ISSN 0013-5194. http://resolver.caltech.edu/CaltechAUTHORS:PEDel96
See Usage Policy.
Use this Persistent URL to link to this item: http://resolver.caltech.edu/CaltechAUTHORS:PEDel96
Median filters are of interest to image processing due to their ability to remove impulsive noise. Conventional digital implementations of the median function, however, require multiple clock cycles, a number that is proportional to the size of the 2-D data block. We present in the Letter a complete CMOS implementation, which consumes very little power and computes the median in just one clock cycle, independently from the size of the data block.
|Additional Information:||© IEE 1996.|
|Subject Keywords:||median filters, filters, image processing, stack|
|Usage Policy:||No commercial reproduction, distribution, display or performance rights in this work are provided.|
|Deposited By:||Tony Diaz|
|Deposited On:||26 Sep 2005|
|Last Modified:||26 Dec 2012 08:41|
Repository Staff Only: item control page