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A 60-Gb/s PAM4 Wireline Receiver with 2-Tap Direct Decision Feedback Equalization Employing Track-and-Regenerate Slicers in 28-nm CMOS

Chen, Kuan-Chang and Kuo, William Wei-Ting and Emami, Azita (2020) A 60-Gb/s PAM4 Wireline Receiver with 2-Tap Direct Decision Feedback Equalization Employing Track-and-Regenerate Slicers in 28-nm CMOS. In: 2020 IEEE Custom Integrated Circuits Conference (CICC). IEEE , Piscataway, NJ, pp. 1-4. ISBN 9781728160313. https://resolver.caltech.edu/CaltechAUTHORS:20200430-151240868

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Abstract

This paper describes a 4-level pulse-amplitude modulation (PAM4) wireline receiver incorporating a continuous time linear equalizer (CTLE) and a 2-tap direct decision feedback equalizer (DFE). A track-and-regenerate CMOS slicer is proposed and employed in the PAM4 receiver. The reduced delay of the proposed slicer and its full-swing outputs allow the implementation of 2-tap direct decision-feedback equalization at 60-Gb/s with improved energy efficiency and area requirements. Fabricated in 28-nm CMOS technology, the PAM4 receiver achieved BER better than 1E-12 at 60-Gb/s with 1.1 pJ/b energy efficiency measured over a channel of 8.2dB loss at Nyquist rate.


Item Type:Book Section
Related URLs:
URLURL TypeDescription
https://doi.org/10.1109/cicc48029.2020.9075948DOIArticle
https://resolver.caltech.edu/CaltechAUTHORS:20201008-083808739Related ItemJournal Article
ORCID:
AuthorORCID
Chen, Kuan-Chang0000-0003-2968-4656
Emami, Azita0000-0003-2608-9691
Additional Information:© 2020 IEEE. The authors would like to thank D. A. Nelson, Caltech MICS lab members and Caltech CHIC lab.
Subject Keywords:wireline; slicer; comparator; PAM4; receiver; track-and-regenerate; equalization; decision feedback; direct feedback
Record Number:CaltechAUTHORS:20200430-151240868
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:20200430-151240868
Official Citation:K. Chen, W. W. Kuo and A. Emami, "A 60-Gb/s PAM4 Wireline Receiver with 2-Tap Direct Decision Feedback Equalization Employing Track-and-Regenerate Slicers in 28-nm CMOS," 2020 IEEE Custom Integrated Circuits Conference (CICC), Boston, MA, USA, 2020, pp. 1-4.
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:102947
Collection:CaltechAUTHORS
Deposited By: George Porter
Deposited On:01 May 2020 14:56
Last Modified:08 Oct 2020 17:06

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