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A 1.6 Gb/s, 3 mW CMOS receiver for optical communication

Emami-Neyestanak, Azita and Liu, Dean and Keeler, Gordon and Helman, Noah and Horowitz, Mark (2002) A 1.6 Gb/s, 3 mW CMOS receiver for optical communication. In: Symposium on VLSI Circuits, Digest of Technical Papers, 2002. IEEE , Piscataway, NJ, pp. 84-87. ISBN 0-7803-7310-3.

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A 1.6 Gb/s receiver for optical communication has been designed and fabricated in a 0.25-μm CMOS process. This receiver has no transimpedance amplifier and uses the parasitic capacitor of the flip-chip bonded photodetector as an integrating element and resolves the data with a double-sampling technique. A simple feedback loop adjusts a bias current to the average optical signal, which essentially "AC couples" the input. The resulting receiver resolves an 11 μA input, dissipates 3 mW of power, occupies 80 μm x 50 μm of area and operates at over 1.6 Gb/s.

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Emami-Neyestanak, Azita0000-0003-2608-9691
Additional Information:© 2002 IEEE. Reprinted with Permission. Publication Date: 13-15 June 2002. The authors would like to thank David A.B. Miller, Diwakar Agarwal, Samuel Palermo, Timothy J. Drabik, Jaeseo Lee, Vladimir Stojanovic, Henrik Johansson for technical discussions and National Semiconductor for fabricating the test chip.
Subject Keywords:CMOS integrated circuits; circuit feedback; digital communication; integrated optoelectronics; mixed analogue-digital integrated circuits; optical receivers; signal sampling; 0.25 micron; 1.6 Gbit/s; 11 muA; 3 mW; 50 micron; 80 micron; CMOS process; CMOS receiver; MQW detector; bias current; double-sampling technique; feedback loop; flip-chip bonded photodetector; optical communication; parasitic capacitor
Record Number:CaltechAUTHORS:EMAvlsic02
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Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:10552
Deposited By: Kristin Buxton
Deposited On:19 May 2008
Last Modified:03 Oct 2019 00:10

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