CaltechAUTHORS
  A Caltech Library Service

A low-power receiver with switched-capacitor summation DFE

Emami-Neyestanak, Azita and Varzaghani, Aida and Bulzacchelli, John and Rylyakov, Alexander and Yang, Chih-Kong Ken and Friedman, Daniel (2006) A low-power receiver with switched-capacitor summation DFE. In: Symposium on VLSI Circuits, 2006. Digest of Technical Papers. IEEE , Piscataway, NJ, pp. 192-193. ISBN 1-4244-0006-6. http://resolver.caltech.edu/CaltechAUTHORS:EMAvlsic06

[img]
Preview
PDF - Published Version
See Usage Policy.

309Kb

Use this Persistent URL to link to this item: http://resolver.caltech.edu/CaltechAUTHORS:EMAvlsic06

Abstract

A low power receiver with a one tap DFE was fabricated in 90mm CMOS technology. The speculative equalization is performed using switched-capacitor-based addition directly at the front-end sample-hold circuit. In order to further reduce the power consumption, an analog multiplexer is used in the speculation technique implementation. A quarter-rate-clocking scheme facilitates the use of low-power front-end circuitry and CMOS clock buffers. At 10Gb/s data rate, the receiver consumes less than 6.0mW from a 1.0V supply.


Item Type:Book Section
Related URLs:
URLURL TypeDescription
https://doi.org/10.1109/VLSIC.2006.1705375DOIArticle
ORCID:
AuthorORCID
Emami-Neyestanak, Azita0000-0003-2608-9691
Additional Information:© 2006 IEEE. Posted online: 2007-02-20. This work was supported by MPO contract H98230-04-C-0920.
Funders:
Funding AgencyGrant Number
Maryland Procurement OfficeH98230-04-C-0920
Subject Keywords:high speed IO; interconnect; receiver; DFE; CMOS integrated circuits; buffer circuits; decision feedback equalizers; low-power electronics; multiplexing equipment; radio receivers; sample and hold circuits; switched capacitor networks; 1.0 V; 10 Gbit/s; 90 nm; CMOS technology; analog multiplexer; clock buffers; front-end sample-hold circuit; low-power receiver; one tap DFE; power consumption; quarter rate clocking scheme; speculative equalization; switched capacitor
Record Number:CaltechAUTHORS:EMAvlsic06
Persistent URL:http://resolver.caltech.edu/CaltechAUTHORS:EMAvlsic06
Alternative URL:http://dx.doi.org/10.1109/VLSIC.2006.1705375
Official Citation:A. Emami-Neyestanak, A. Varzaghani, J. Bulzacchelli, A. Rylyakov, C. -. Yang and D. Friedman, "A Low-Power Receiver with Switched-Capacitor Summation DFE," 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers., Honolulu, HI, 2006, pp. 192-193. doi: 10.1109/VLSIC.2006.1705375
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:10577
Collection:CaltechAUTHORS
Deposited By: Kristin Buxton
Deposited On:19 May 2008
Last Modified:04 Mar 2019 22:11

Repository Staff Only: item control page