Palermo, Samuel and Emami-Neyestanak, Azita and Horowitz, Mark (2007) A 90nm CMOS 16Gb/s transceiver for optical interconnects. In: IEEE International Solid-State Circuits Conference (ISSCC 2007), Digest of Technical Papers. San Francisco, CA. IEEE , Piscataway, NJ, 44-45, 586. ISBN 1424408539. https://resolver.caltech.edu/CaltechAUTHORS:PALisscc07
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Abstract
An optical interconnect transceiver incorporates a 4-tap FIR TX to reduce VCSEL average current and an integrating/double-sampling RX to eliminate the need for a bit-rate TIA. A dual-loop CDR with baud-rate phase detection further reduces power and area. Fabricated in a 1V 90nm CMOS process, the transceiver achieves 16Gb/s operation while consuming 129mW and occupying 0.105mm^2.
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| Additional Information: | © 2000 IEEE. Reprinted with permission. Publication Date: 11-15 Feb. 2007. The authors would like to acknowledge the help and support of D. Patil, B. Nezamfar, P. Chiang, and B. Gupta, CMP and STMicroelectronics for chip fabrication, ULM photonics for VCSELs, Albis Optoelectronics for photodiodes, and MARCO-IFC for funding. | ||||||
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| Subject Keywords: | CMOS integrated circuits; integrated optoelectronics; optical interconnections; optical receivers; optical transmitters; surface emitting lasers; transceivers; 1 V; 129 mW; 16 Gbit/s; 90 nm; CMOS process; VCSEL; baud-rate phase detection; optical interconnect transceiver; vertical cavity surface emitting lasers | ||||||
| DOI: | 10.1109/ISSCC.2007.373579 | ||||||
| Record Number: | CaltechAUTHORS:PALisscc07 | ||||||
| Persistent URL: | https://resolver.caltech.edu/CaltechAUTHORS:PALisscc07 | ||||||
| Usage Policy: | No commercial reproduction, distribution, display or performance rights in this work are provided. | ||||||
| ID Code: | 10797 | ||||||
| Collection: | CaltechAUTHORS | ||||||
| Deposited By: | Kristin Buxton | ||||||
| Deposited On: | 11 Jun 2008 | ||||||
| Last Modified: | 08 Nov 2021 21:11 |
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