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TSV-Last Integration to Replace ASIC Wire Bonds in the Assembly of X-Ray Detector Arrays

Hicks, Jennifer Ovental and Malta, Dean and Bordelon, David and Richter, Daniel and Hong, Jaesub and Grindlay, Jonathan and Allen, Branden and Violette, Daniel P. and Miyasaka, Hiromasa (2021) TSV-Last Integration to Replace ASIC Wire Bonds in the Assembly of X-Ray Detector Arrays. In: 2021 IEEE 71st Electronic Components and Technology Conference (ECTC). IEEE , Piscataway, NJ, pp. 170-177. ISBN 978-1-6654-4097-4. https://resolver.caltech.edu/CaltechAUTHORS:20211123-164455637

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Abstract

This paper will describe the use of through-silicon vias (TSVs) in a readout application-specific integrated circuit (ASIC) chip to replace wire bonds in the assembly of cadmium zinc telluride (CZT) X-ray detector arrays for space telescope applications. The TSV packaging approach includes solder bump connections from the back of the ASIC to the underlying board. This approach will greatly reduce the spacing between adjacent detectors in an array, eliminate potential damage to wires during assembly, and avoid any interference, which the wires can pick up during operation. We report a TSV-last integration process for the mixed signal ASIC chip used to read signals from the CZT detectors. The TSVs were integrated into existing ASIC wafers without any required redesign, and formed as blind vias from the frontside of the ASIC in metal-free areas adjacent to the wire bond pads. The TSVs were then connected to the bond pads using a routing metal layer. The wafers were bonded to temporary carriers and thinned from the backside, revealing the TSVs. After forming the redistribution lines (RDL) and under bump metallization (UBM), the wafers were released from the carriers and solder bumps were attached for subsequent assembly processes. In the sections that follow, we will review the details of the ASIC wafer post-processing, including TSV fabrication, wafer thinning, frontside and backside metallization layers, and solder bumping. We will report electrical testing of TSV daisy chains and isolation test structures. Also, results of ASIC functionality testing, performed before and after TSV insertion, will be discussed.


Item Type:Book Section
Related URLs:
URLURL TypeDescription
http://doi.org/10.1109/ectc32696.2021.00038DOIArticle
ORCID:
AuthorORCID
Hong, Jaesub0000-0002-6089-5390
Grindlay, Jonathan0000-0002-1323-5314
Additional Information:© 2021 IEEE. This work was supported with funding from NASA APRA grant NNX17AE62G. The authors wish to thank additional Micross technical staff members who supported the wafer processing and SEM characterization, in particular Pedro Colón and Dana Fox. We would also like to acknowledge Syagrus Systems for temporary bonding/thinning/debonding support, Entrepix for CMP processing, and Hionix for ionized PVD support.
Funders:
Funding AgencyGrant Number
NASANNX17AE62G
Subject Keywords:Through-silicon via, TSV, 3D Integration, X-ray detector, CdZnTe, CZT
DOI:10.1109/ectc32696.2021.00038
Record Number:CaltechAUTHORS:20211123-164455637
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:20211123-164455637
Official Citation:J. O. Hicks et al., "TSV-Last Integration to Replace ASIC Wire Bonds in the Assembly of X-Ray Detector Arrays," 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), 2021, pp. 170-177, doi: 10.1109/ECTC32696.2021.00038
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:112001
Collection:CaltechAUTHORS
Deposited By: Tony Diaz
Deposited On:23 Nov 2021 17:01
Last Modified:23 Nov 2021 17:01

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