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A 16-Channel Neural Recording System-on-Chip With CHT Feature Extraction Processor in 65-nm CMOS

Uran, Arda and Ture, Kerim and Aprile, Cosimo and Trouillet, Alix and Fallegger, Florian and Revol, Emilie C. M. and Emami, Azita and Lacour, Stéphanie P. and Dehollain, Catherine and Leblebici, Yusuf and Cevher, Volkan (2022) A 16-Channel Neural Recording System-on-Chip With CHT Feature Extraction Processor in 65-nm CMOS. IEEE Journal of Solid-State Circuits . ISSN 0018-9200. doi:10.1109/jssc.2022.3161296. (In Press) https://resolver.caltech.edu/CaltechAUTHORS:20220407-668501590

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Abstract

Next-generation invasive neural interfaces require fully implantable wireless systems that can record from a large number of channels simultaneously. However, transferring the recorded data from the implant to an external receiver emerges as a significant challenge due to the high throughput. To address this challenge, this article presents a neural recording system-on-chip that achieves high resource and wireless bandwidth efficiency by employing on-chip feature extraction. Energy-area-efficient 10-bit 20-kS/s front end amplifies and digitizes the neural signals within the local field potential (LFP) and action potential (AP) bands. The raw data from each channel are decomposed into spectral features using a compressed Hadamard transform (CHT) processor. The selection of the features to be computed is tailored through a machine learning algorithm such that the overall data rate is reduced by 80% without compromising classification performance. Moreover, the CHT feature extractor allows waveform reconstruction on the receiver side for monitoring or additional post-processing. The proposed approach was validated through in vivo and off-line experiments. The prototype fabricated in 65-nm CMOS also includes wireless power and data receiver blocks to demonstrate the energy and area efficiency of the complete system. The overall signal chain consumes 2.6 μW and occupies 0.021 mm² per channel, pointing toward its feasibility for 1000-channel single-die neural recording systems.


Item Type:Article
Related URLs:
URLURL TypeDescription
https://doi.org/10.1109/jssc.2022.3161296DOIArticle
ORCID:
AuthorORCID
Uran, Arda0000-0002-8762-4494
Ture, Kerim0000-0003-3531-140X
Aprile, Cosimo0000-0002-6558-7688
Trouillet, Alix0000-0002-4242-0324
Fallegger, Florian0000-0003-0626-5264
Revol, Emilie C. M.0000-0002-8483-2239
Emami, Azita0000-0002-6945-9958
Dehollain, Catherine0000-0002-6262-2644
Additional Information:© 2022 IEEE. Manuscript received July 16, 2021; revised October 16, 2021, December 10, 2021, and January 26, 2022; accepted March 10, 2022. This article was approved by Associate Editor Farhana Sheikh. This work was supported in part by the European Research Council (ERC) through the European Union’s Horizon 2020 Research and Innovation Programme under Grant 725594, in part by the Hasler Foundation under Project 16066, in part by the Bertarelli Foundation, in part by the Swiss National Science Foundation (SNSF) Bridge under Grant 40B1-0_193764, in part by the SNSF Sinergia under Grant CRSII5_183519, in part by the Wyss Center, and in part by Innosuisse under Grant 41945.1 IP-LS. This work involved human subjects or animals in its research. Approval of all ethical and experimental procedures and protocols was granted by the Veterinary Office of the Canton of Geneva, Switzerland, under License Nos. 32846 and 33223, and performed in line with the Regulations of the Animal Welfare Act (SR 455) and Animal Welfare Ordinance (SR 455.1).
Funders:
Funding AgencyGrant Number
European Research Council (ERC)725594
Hasler Foundation16066
Bertarelli FoundationUNSPECIFIED
Swiss National Science Foundation (SNSF)40B1-0_193764
Swiss National Science Foundation (SNSF)CRSII5_183519
Wyss CenterUNSPECIFIED
Swiss Innovation Agency41945.1 IP-LS
Subject Keywords:Compressed Hadamard transform (CHT), implantable system-on-chip (SoC), machine learning (ML), neural recording, resource efficiency, seizure detection, spreading depolarization (SD), wireless power and data transfer (WPDT)
DOI:10.1109/jssc.2022.3161296
Record Number:CaltechAUTHORS:20220407-668501590
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:20220407-668501590
Official Citation:A. Uran et al., "A 16-Channel Neural Recording System-on-Chip With CHT Feature Extraction Processor in 65-nm CMOS," in IEEE Journal of Solid-State Circuits, doi: 10.1109/JSSC.2022.3161296.
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:114192
Collection:CaltechAUTHORS
Deposited By: George Porter
Deposited On:07 Apr 2022 09:58
Last Modified:08 Apr 2022 14:56

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  • A 16-Channel Neural Recording System-on-Chip With CHT Feature Extraction Processor in 65-nm CMOS. (deposited 07 Apr 2022 09:58) [Currently Displayed]

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  • Uran, Arda and Ture, Kerim and Aprile, Cosimo and Trouillet, Alix and Fallegger, Florian and Revol, Emilie C. M. and Emami, Azita and Lacour, Stéphanie P. and Dehollain, Catherine and Leblebici, Yusuf and Cevher, Volkan A 16-Channel Neural Recording System-on-Chip With CHT Feature Extraction Processor in 65-nm CMOS. (deposited 07 Apr 2022 09:58) [Currently Displayed]

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