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Stochastic switching circuit synthesis

Wilhelm, Daniel and Bruck, Jehoshua (2008) Stochastic switching circuit synthesis. In: IEEE International Symposium on Information Theory (ISIT '08), Toronto, Canada, 6-11 July 2008. IEEE , Piscataway, NJ, pp. 1388-1392. ISBN 978-1-4244-2571-6. https://resolver.caltech.edu/CaltechAUTHORS:WILisit08

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Abstract

Shannon in his 1938 Masterpsilas Thesis demonstrated that any Boolean function can be realized by a switching relay circuit, leading to the development of deterministic digital logic. Here, we replace each classical switch with a probabilistic switch (pswitch). We present algorithms for synthesizing circuits closed with a desired probability, including an algorithm that generates optimal size circuits for any binary fraction. We also introduce a new duality property for series-parallel stochastic switching circuits. Finally, we construct a universal probability generator which maps deterministic inputs to arbitrary probabilistic outputs. Potential applications exist in the analysis and design of stochastic networks in biology and engineering.


Item Type:Book Section
Related URLs:
URLURL TypeDescription
http://dx.doi.org/10.1109/ISIT.2008.4595215DOIUNSPECIFIED
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4595215PublisherUNSPECIFIED
ORCID:
AuthorORCID
Bruck, Jehoshua0000-0001-8474-0812
Additional Information:© Copyright 2008 IEEE. Reprinted with permission. Date Published in Issue: 2008-08-08.
Subject Keywords:network synthesis; relays; stochastic processes; switching circuits
Record Number:CaltechAUTHORS:WILisit08
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:WILisit08
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:11758
Collection:CaltechAUTHORS
Deposited By: Archive Administrator
Deposited On:23 Sep 2008 16:59
Last Modified:22 Nov 2019 09:58

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