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Complementary Symmetry Nanowire Logic Circuits: Experimental Demonstrations and in Silico Optimizations

Sheriff, Bonnie A. and Wang, Dunwei and Heath, James R. and Kurtin, Juanita N. (2008) Complementary Symmetry Nanowire Logic Circuits: Experimental Demonstrations and in Silico Optimizations. ACS Nano, 2 (9). pp. 1789-1798. ISSN 1936-086X. https://resolver.caltech.edu/CaltechAUTHORS:SHEacsn08

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Abstract

Complementary symmetry (CS) Boolean logic utilizes both p- and n-type field-effect transistors (FETs) so that an input logic voltage signal will turn one or more p- or n-type FETs on, while turning an equal number of n- or p-type FETs off. The voltage powering the circuit is prevented from having a direct pathway to ground, making the circuit energy efficient. CS circuits are thus attractive for nanowire logic, although they are challenging to implement. CS logic requires a relatively large number of FETs per logic gate, the output logic levels must be fully restored to the input logic voltage level, and the logic gates must exhibit high gain and robust noise margins. We report on CS logic circuits constructed from arrays of 16 nm wide silicon nanowires. Gates up to a complexity of an XOR gate (6 p-FETs and 6 n-FETs) containing multiple nanowires per transistor exhibit signal restoration and can drive other logic gates, implying that large scale logic can be implemented using nanowires. In silico modeling of CS inverters, using experimentally derived look-up tables of individual FET properties, is utilized to provide feedback for optimizing the device fabrication process. Based upon this feedback, CS inverters with a gain approaching 50 and robust noise margins are demonstrated. Single nanowire-based logic gates are also demonstrated, but are found to exhibit significant device-to-device fluctuations.


Item Type:Article
Related URLs:
URLURL TypeDescription
http://dx.doi.org/10.1021/nn800025qDOIArticle
ORCID:
AuthorORCID
Heath, James R.0000-0001-5356-4385
Additional Information:© 2008 American Chemical Society. Received for review January 13, 2008 and accepted August 1, 2008. Published online August 12, 2008. This work was supported in part by the by the NSF (Grant CCF-0541461), the MARCO Center for Advanced Materials and Devices, and a subcontract from the MITRE Corporation. We thank A. DeHon, A. Martin, J. Lee, K. Bowman, Pillarisetty, Raychowdhury, and B. Kean for insightful discussion, H. Ahmad for graphics assistance, F. Brewer for MEDICI access, and Synopsys, Inc. for software donation. B.A.S. acknowledges an Intel Foundation Ph.D. Fellowship award.
Funders:
Funding AgencyGrant Number
NSFCCF-0541461
Microelectronics Advanced Research Corporation (MARCO)UNSPECIFIED
MITRE CorporationUNSPECIFIED
Intel FoundationUNSPECIFIED
Subject Keywords:nanotechnology; complementary circuits; nanowire; field effect transistors; circuit simulations
Issue or Number:9
Record Number:CaltechAUTHORS:SHEacsn08
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:SHEacsn08
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:12138
Collection:CaltechAUTHORS
Deposited By: Archive Administrator
Deposited On:24 Oct 2008 22:57
Last Modified:03 Oct 2019 00:25

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