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All-Digital CDR for High-Density, High-Speed I/O

Loh, Matthew and Emami-Neyestanak, Azita (2010) All-Digital CDR for High-Density, High-Speed I/O. In: 2010 Symposium on VLSI Circuits. Symposium on VLSI Circuits-Digest of Papers . IEEE , pp. 147-148. ISBN 978-1-4244-7636-7.

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A novel all-digital CDR for source-synchronous links, and its implementation in 90nm CMOS, is presented. A phase alignment technique with ping-pong action between two clock phases is used. The system is implemented in static CMOS logic, occupies 0.234 mm^2 and dissipates 16.6 mW at 6 Gb/s, demonstrating BER < 10^(-13) with PRBS-7 input. The compactness and all-static-CMOS nature of the system make it suitable for use in high-speed I/Os requiring per-pin synchronization.

Item Type:Book Section
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Emami-Neyestanak, Azita0000-0003-2608-9691
Additional Information:© 2010 IEEE. Issue Date: 16-18 June 2010. Date of Current Version: 02 September 2010.
Subject Keywords:CDR; static CMOS; all-digital
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INSPEC Accession Number11515693
Series Name:Symposium on VLSI Circuits-Digest of Papers
Record Number:CaltechAUTHORS:20110329-081801877
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Official Citation:Loh, M.; Emami-Neyestanak, A.; , "All-digital CDR for high-density, high-speed I/O," VLSI Circuits (VLSIC), 2010 IEEE Symposium on , vol., no., pp.147-148, 16-18 June 2010 doi: 10.1109/VLSIC.2010.5560319 URL:
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:23146
Deposited By: Tony Diaz
Deposited On:25 May 2011 19:42
Last Modified:03 Oct 2019 02:43

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