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Can asynchronous techniques help the SoC designer?

Martin, Alain J. (2006) Can asynchronous techniques help the SoC designer? In: IFIP VLSI-SoC 2006: IFIP TC 10/WG 10.5 International Conference on Very Large Scale Integration & System-on-Chip. IEEE , Piscataway, NJ, pp. 7-11. ISBN 978-3-901882-19-7.

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As technological advances make it possible to integrate an entire system on a single die, the designer of a system-on-chip (SoC) is confronted with increasing difficulties concerning complexity, reliability, energy and power consumption, and clock distribution. All those issues are aggravated by increasing parameters variability as a result of the same technological advances. This paper argues that because of the quasi-independence of asynchronous (QDI) circuits of timing, asynchronous logic alleviates the problems posed by parameter variability, and eliminates the clock distribution problem altogether. Furthermore, as some researchers attempt to turn the liability into an asset by exploiting parameter variability to design truly probabilistic computation, the flexibility and time-independence of asynchronous logic could be a natural match.

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Additional Information:© 2006 IEEE. Issue Date: 16-18 Oct. 2006. Date of Current Version: 20 February 2007. The research described in this paper was sponsored by the Defense Research Project Agency, and monitored by the Air Force of Scientific Research.
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Defense Advanced Research Projects Agency (DARPA)UNSPECIFIED
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INSPEC Accession Number9442134
Record Number:CaltechAUTHORS:20110722-095429816
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Official Citation:Martin, A.J.; , "Can Asynchronous Techniques Help the SoC Designer?," Very Large Scale Integration, 2006 IFIP International Conference on , vol., no., pp.7-11, 16-18 Oct. 2006 doi: 10.1109/VLSISOC.2006.313284
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:24502
Deposited By: Ruth Sustaita
Deposited On:22 Jul 2011 17:26
Last Modified:09 Nov 2021 16:24

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