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Fault Secure Encoder and Decoder for Memory Applications

Naeimi, Helia and DeHon, André (2007) Fault Secure Encoder and Decoder for Memory Applications. In: 2007 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems. IEEE , Los Alamitos, CA, pp. 409-417. ISBN 978-0-7695-2885-4. https://resolver.caltech.edu/CaltechAUTHORS:20110817-152509198

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Abstract

We introduce a reliable memory system that can tolerate multiple transient errors in the memory words as well as transient errors in the encoder and decoder (corrector) circuitry. The key novel development is the fault-secure detector (FSD) error-correcting code (ECC) definition and associated circuitry that can detect errors in the received encoded vector despite experiencing multiple transient faults in its circuitry. The structure of the detector is general enough that it can be used for any ECC that follows our FSD-ECC definition. We prove that two known classes of Low-Density Parity-Check Codes have the FSD-ECC property: Euclidean Geometry and Projective Geometry codes. We identify a specific FSD-LDPC code that can tolerate up to 33 errors in each memory word or supporting logic that requires only 30% area overhead for memory blocks of 10 Kbits or larger. Larger codes can achieve even higher reliability and lower area overhead. We quantify the importance of protecting encoder and decoder (corrector) circuitry and illustrate a scenario where the system failure rate (FIT) is dominated by the failure rate of the encoder and decoder.


Item Type:Book Section
Related URLs:
URLURL TypeDescription
http://dx.doi.org/10.1109/DFT.2007.54DOIUNSPECIFIED
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4358410PublisherUNSPECIFIED
Additional Information:© 2007 IEEE. Issue Date: 26-28 Sept. 2007; Date of Current Version: 22 October 2007. We would like to thank Dr. Shalini Gohsh for her valuable reference to EG-LDPCs, and Benjamin Gojman for the discussion leading to the optimized majority gate implementation. This research was funded in part by National Science Foundation Grant CCF-0403674 and the Defense Advanced Research Projects Agency under ONR contract N00014-01-0651. This material is based upon work supported by the Department of the Navy, Office of Naval Research. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the National Science Foundation or the Office of Naval Research.
Funders:
Funding AgencyGrant Number
NSFCCF-0403674
Defense Advanced Research Projects Agency (DARPA)N00014-01-0651
Office of Naval Research (ONR)UNSPECIFIED
Other Numbering System:
Other Numbering System NameOther Numbering System ID
INSPEC Accession Number9870441
DOI:10.1109/DFT.2007.54
Record Number:CaltechAUTHORS:20110817-152509198
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:20110817-152509198
Official Citation:Naeimi, H.; DeHon, A.; , "Fault Secure Encoder and Decoder for Memory Applications," Defect and Fault-Tolerance in VLSI Systems, 2007. DFT '07. 22nd IEEE International Symposium on , vol., no., pp.409-417, 26-28 Sept. 2007 doi: 10.1109/DFT.2007.54
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:24921
Collection:CaltechAUTHORS
Deposited By: Jason Perez
Deposited On:18 Aug 2011 18:05
Last Modified:09 Nov 2021 16:27

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