Tierno, Jose A. and Martin, Alain J. (1994) Low-Energy Asynchronous Memory Design. Computer Science Technical Reports, California Institute of Technology , Pasadena, CA. (Unpublished) https://resolver.caltech.edu/CaltechCSTR:1994.cs-tr-94-21
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Abstract
We introduce the concept of energy per operation as a measure of performance of an asynchronous circuit. We show how to model energy consumption based on the high-level language specification. This model is independent of voltage and timing considerations. We apply this model to memory design. We show first how to dimension a memory array, and how to break up this memory array into smaller arrays to minimize the energy per access. We then show how to use cache memory and pre-fetch mechanisms to further reduce energy per access.
| Item Type: | Report or Paper (Technical Report) | ||||||
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| Additional Information: | © 1994 California Institute of Technology. The research described in this paper was sponsored by the Advanced Research Projects Agency ARPA Order number 6202 and monitored by the Office of Naval Research under contract number N00014-87-K-0745. | ||||||
| Group: | Computer Science Technical Reports | ||||||
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| Subject Keywords: | Low energy; low power; asynchronous design; memory design | ||||||
| Series Name: | Computer Science Technical Reports | ||||||
| DOI: | 10.7907/Z9X9289S | ||||||
| Record Number: | CaltechCSTR:1994.cs-tr-94-21 | ||||||
| Persistent URL: | https://resolver.caltech.edu/CaltechCSTR:1994.cs-tr-94-21 | ||||||
| Usage Policy: | You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format. | ||||||
| ID Code: | 26875 | ||||||
| Collection: | CaltechCSTR | ||||||
| Deposited By: | Imported from CaltechCSTR | ||||||
| Deposited On: | 14 May 2001 | ||||||
| Last Modified: | 03 Oct 2019 03:18 |
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