A Caltech Library Service

Pipelined Asynchronous Cache Design

Nyströem, Mika (1997) Pipelined Asynchronous Cache Design. California Institute of Technology , Pasadena, CA. (Unpublished)

Postscript - Submitted Version
See Usage Policy.

[img] PDF (Thesis Degree of Master of Science) - Submitted Version
See Usage Policy.


Use this Persistent URL to link to this item:


This thesis describes the development of pipelined asynchronous cache memories. The work is done in the context of the performance characteristics of memories and transistor logic of a late 1990's high-performance asynchronous microprocessor. We describe the general framework of asynchronous memory systems, caching, and those system characteristics that make caching of growing importance and keep it an interesting research topic. Finally, we present the main contribution of this work, which is a latency-tolerating asynchronous cache micro-architecture suitable for asynchronous microprocessors. In Chapter Two, we present a case study of the Level 1 data and instruction caches for the Caltech MiniMIPS asynchronous microprocessor, currently under development at Caltech. The implementation is quasi-delay-insensitive in 0.6 micron scalable CMOS rules, with a logic latency of approximately 2 nanoseconds.

Item Type:Report or Paper (Technical Report)
Additional Information:© 1997 California Institute of Technology. I wish to thank the past and present members of the Asynchronous VLSI Group at Caltech for many stimulating discussions: Paul Pénzes, Robert Southworth, Marcel van der Goot, Tony Lee, Peter Hofstee, José Tierno, Uri Cummings, and especially Andrew Lines, whose comments inspired much of the work described in this thesis and Rajit Mahomar, whose help with TEXnicalities, among many other things, made it at all possible. Last but not least, thanks to Alain Martin for being my advisor and putting up with the many odd ideas I have had. The work described in this thesis was sponsored by the Defense Advanced Research Projects Agency and monitored by the Office of Army Research. It was also supported in part by Okawa Foundation Fellowship. This work would not have been possible without the work of many hundreds of programmers who indirectly supported it with free soft ware such Berkeley's magic and BSD operating system, Donald Knuth's TEX, and too many minor utility programs to mention.
Group:Computer Science Technical Reports
Funding AgencyGrant Number
Okawa FoundationUNSPECIFIED
Defense Advanced Research Projects Agency (DARPA)UNSPECIFIED
Subject Keywords:asynchronous vlsi; qdi; quasi delay-insensitive; CMOS; pipelined cache design; low-power
Record Number:CaltechCSTR:2001.009
Persistent URL:
Usage Policy:You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.
ID Code:26919
Deposited By: Imported from CaltechCSTR
Deposited On:12 Dec 2001
Last Modified:03 Oct 2019 03:19

Repository Staff Only: item control page