Pénzes, Paul I. and Martin, Alain J. (2001) Global and local properties of asynchronous circuits optimized for energy efficiency. California Institute of Technology , Pasadena, CA. (Unpublished) https://resolver.caltech.edu/CaltechCSTR:2002.002
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Abstract
In this paper we explore global and local properties of asynchronous circuits sized for the energy efficiency metric Et^2. We develop a theory that enables an abstract view on transistor sizing. These results allow us to accurately estimate circuit performance and compare circuit design choices at logic gate level without going through the costly sizing process. We estimate that the improvement in energy efficiency due to sizing is 2 to 3.5 times when compared to a design optimized for speed.
| Item Type: | Report or Paper (Technical Report) | ||||||
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| Additional Information: | © 2001 California Institute of Technology. We wish to thank the members of the Asynchronous VLSI Group at Caltech for many stimulating discussions: Mika Nyström Catherine Wong and Karl Papadantonakis and José Tierno from IBM TJ Watson Research Center. The research described in this paper was sponsored by the Defense Advanced Research Projects Agency and monitored by the Air Force under contract F29601-00-K-0184. | ||||||
| Group: | Computer Science Technical Reports | ||||||
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| Subject Keywords: | asynchronous, transistor sizing | ||||||
| DOI: | 10.7907/Z9FJ2DSS | ||||||
| Record Number: | CaltechCSTR:2002.002 | ||||||
| Persistent URL: | https://resolver.caltech.edu/CaltechCSTR:2002.002 | ||||||
| Usage Policy: | You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format. | ||||||
| ID Code: | 26925 | ||||||
| Collection: | CaltechCSTR | ||||||
| Deposited By: | Imported from CaltechCSTR | ||||||
| Deposited On: | 11 Apr 2002 | ||||||
| Last Modified: | 03 Oct 2019 03:19 |
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