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Transistor Sizing of Energy-Delay-Efficient Circuits

Pénzes, Paul I. and Nyströem, Mika and Martin, Alain J. (2002) Transistor Sizing of Energy-Delay-Efficient Circuits. California Institute of Technology , Pasadena, CA. (Unpublished)

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This paper studies the problem of transistor sizing of CMOS circuits optimized for energy-delay efficiency, i.e., for optimal Et^n where E is the energy consumption and t is the delay of the circuit, while n is a fixed positive optimization index that reflects the chosen trade-off between energy and delay. We propose a set of analytical formulas that closely approximate the optimal transistor sizes. We then study an efficient iteration procedure that can further improve the original analytical solution. Based on these results, we introduce a novel transistor sizing algorithm for energy-delay efficiency.

Item Type:Report or Paper (Technical Report)
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Additional Information:© 2002 California Institute of Technology. The authors thank Catherine Wong and Karl Papadantonakis for many stimulating discussions. The research reported in this paper was sponsored by the Defense Advanced Research Projects Agency and monitored by the Air Force under contract F29601-00-K-0184.
Group:Computer Science Technical Reports
Funding AgencyGrant Number
Air Force Office of Scientific Research (AFOSR)F29601-00-K-0184
Defense Advanced Research Projects Agency (DARPA)UNSPECIFIED
Subject Keywords:transistor sizing
Record Number:CaltechCSTR:2002.003
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Usage Policy:You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.
ID Code:26926
Deposited By: Imported from CaltechCSTR
Deposited On:11 Apr 2002
Last Modified:03 Oct 2019 03:19

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