Switch-Level Fault Simulation of MOS Digital Circuits

Abstract

Thls thesis presents an algorithm for fault simulation of metal-oxide-semiconductor (MOS), field-effect transistor (FET) digital circuits. The circuits are modeled at the switch-level as networks of charge storage nodes connected with bidirectional transistor switches. Since the transistor structure of a NOS circuit is explicitly represented by its switch-level network, and since the circuit's logical behavior is modeled directly, the algorithm describes the behavior of defective MOS circuits with more accuracy than is possible with traditional logic gate fault simulation techniques. The algorithm is capable of analyzing a variety of MOS circuit defects including the classical stuck-at-zero and stuck-at-one node faults, stuck-open and stuck-closed transistor faults, and resistive short and open faults in wires. By using the concurrent simulation technique, the algorithm requires far less computation than a simple serial simulation of each defective circuit.