A Caltech Library Service

HEX: A Hierarchical Circuit Extractor

Oyang, Yen-Jen (1984) HEX: A Hierarchical Circuit Extractor. California Institute of Technology , Pasadena, CA. (Unpublished)

Postscript - Accepted Version
See Usage Policy.

[img] PDF - Accepted Version
See Usage Policy.


Use this Persistent URL to link to this item:


This report describes the algorithm, implementation, and performance of a hierarchical circuit extractor, HEX, for Metal-Oxide Semiconductor(M0S) layout designs at Caltech. The input to HEX is a layout design in Caltech intermediate Form(CIF), a hierarchical layout description language, and the output is a hierarchical netlist describing the circuit. HEX avoids redundant work by finding out the repetitive cells in the input CIF file. To handle overlapping instances, HEX modifies the hierarchy in the CIF file to generate a new one without overlapping instances. HEX then traverses the resulting hierarchical structure, calls a flat extractor to extract leaf cells and composes cells bottom up to get the circuit information of the whole chip.

Item Type:Report or Paper (Technical Report)
Group:Computer Science Technical Reports
Record Number:CaltechCSTR:1984.5139-tr-84
Persistent URL:
Usage Policy:You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.
ID Code:26942
Deposited By: Imported from CaltechCSTR
Deposited On:25 Jul 2002
Last Modified:03 Oct 2019 03:19

Repository Staff Only: item control page