RTsim: A register transfer simulator

Abstract

The growing complexity and size of VLSI processors are demanding extremely accurate, yet efficient, simulation facilities for microcode debugging, logic verification, and system integration. However, reliance on mask iterations to remedy problems on a chip not only raises costs, but also extends the design cycle. Simulation justifies itself in both the turn around time and the design cost. Gate level simulation is one method for reducing errors in a chip design. However, gate level simulation of large designs are extremely expensive, and sometimes impossible when the gate level representation is not known. This thesis attempts to solve this problem by providing a functional level approach, consisting of a register transfer description language, an embedded functional modeling language, a reconfigurable assembler, and a functional simulation program. Mixed-level simulation capability is also provided by allowing the replacement of a functional unit by a transistor network which is being simulated by a switch-level logic simulator.