Signal Delay in General RC Networks with Application to Timing Simulation of Digital Integrated Circuits

Abstract

Modeling digital MOS circuits by RC networks has become a well accepted practice for estimating delays. In 1981, Penfield and Rubinstein proposed a method to bound the delays of the nodes in an RC tree network. In this paper, we address the problem of dynamic timing simulation under RC-based models. Based upon the delay of Elmore, a single value of delay is derived for any node in a general RC network. The effects of parallel connections and stored charges are properly taken into consideration. The algorithm can be used either as a stand-alone simulator, or as a front end for producing initial waveforms for waveform-relaxation based circuit simulators. An experimental simulator called SDS (Signal Delay Simulator) has been developed. For all the examples tested so far, this simulator runs about two to three orders of magnitude faster than SPICE, and detects all transitions and glitches at approximately the correct time.