PLASYS: Final Report

Abstract

This Silicon Structure Project Report documents an exploratory study of Programmable Logic Array (PLA) optimization. In section I, the report introduces PLAs, and discusses five areas of possible optimization - system design, logic design, circuit design, layout, and fabrication and test. Section II continues with a description of the logic design optimization techniques investigated during this study. Section III is the Users' Guide for the PLA optimization system developed as part of this work. Finally, Section IV presents some conclusions. The two main conclusions concern the effectiveness of the PLASYS logic optimizations, and the potential applications for PLASYS. 1. Effectiveness - The PLASYS optimizations are not on a par with hand optimization. PLASYS will perform most straight forward optimizations, and remove most trivial coding inefficiencies. However, it can not find the optimal PLA coding. It is fair to compare PLASYS with an average present-day compiler. It does not discover all possible optimizations; however, it does make most of the obvious improvements. It performs operations analogous constant term evaluation, and recognition of common sub-expressions and redundant calculations. 2. Application - The primary application for PLASYS is PLAs which can afford to give area for other considerations. Other considerations could include: o Shortened Design Time - This might be to allow many higher-level design iterations, or to reduce total development time. o Higher Level Specification - The need for higher level PLA specification might be to better document the design, or to reduce its complexity, thus increasing the confidence in its correctness. The report also contains five appendicies. These appendices document both the tabular and higher-level specifications languages for PLAs. Appendix III gives two examples of PLA design, Appendix IV provides system documentation. Appendix V is a PLA optimization Bibliography.