Modeling and Verification in Structured Integrated Circuit Design

Abstract

Traditional design tools based on geometric representations do not provide an adequate base from which to construct and verify silicon implementations of complex systems. More comprehensive structural, physical and behavioural descriptions must be developed from appropriate representations. This thesis proposes models which may be used to construct unified and consistent descriptions of the structural, physical and behavoural attributes of a design. It also discusses a method of capturing these descriptions using a textual representation embedded in an object oriented programming language. A range of subsytems have been implemented within a design environment tailored to the proposed models of the design activitiy. In addition to the typical graphical feedback and mask making oriented output a comprehensibe list of verificaiton procedures has been integrated into the system. These include dimensional design rule checking, electrical calculations, connectivity verification and simulation at a number of levels of abstraction.