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A Fault Tolerant Integrated Circuit Memory

Barton, Anthony Francis (1980) A Fault Tolerant Integrated Circuit Memory. Computer Science Technical Reports, 1980.3761. California Institute of Technology , Pasadena, CA. (Unpublished) http://resolver.caltech.edu/CaltechCSTR:1980.3761-tr-80

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Abstract

Most commercially produced integrated circuits are incapable of tolerating manufacturing defects. The area and function of the circuits is thus limited by the probability of faults occurring within the circuit. This thesis examines techniques for using redundancy in memory circuits to provide fault tolerance and to increase storage capacity. A hierarchical memory architecture using multiple Hamming codes is introduced and analysed to determine its resistance to manufacturing defects. The results of the analysis indicate that substantial yield improvement is possible with relatively modest increases in circuit area. Also, the architecture makes it possible to build larger memory circuits than is economically feasible without redundancy.


Item Type:Report or Paper (Technical Report)
Group:Computer Science Technical Reports
Funders:
Funding AgencyGrant Number
Defense Advanced Research Project Agency (DARPA)3771
Office of Naval Research (ONR)N00014-79-C-0597
Record Number:CaltechCSTR:1980.3761-tr-80
Persistent URL:http://resolver.caltech.edu/CaltechCSTR:1980.3761-tr-80
Usage Policy:You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.
ID Code:27057
Collection:CaltechCSTR
Deposited By: Imported from CaltechCSTR
Deposited On:02 Jan 2003
Last Modified:12 Mar 2018 18:20

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