Structure, placement and modelling

Abstract

The nature of hierarchical design tools for VLSI implementation is explored in terms of the "Caltech Structured Design Philosophy" as interpreted by Rowson in his doctoral thesis [Rowson]. One obvious implication of this thesis is the desirability of tools for leaf and composition cell design. This thesis describes one such tool targeted at the composition cell design problem. It is intended to be used in the architectual phases of a design and allows structural (interface specification), physical (floor planing), and behavioral (simulation modelling) descriptions to be written down, integrated, and tested. One biproduct of this process is the generation of a comprehensive design document from which workbooks can be generated automatically. The later sections describe a hierarchical simulator and how it fits into the step-wise refinement process of design. The most important considerations in the design of this simulator were ease of expression and the provision of enough generality to allow the specification of any VLSI structure. Simulation takes place in a time axis/delay environment and uses a system in which nodes may take one of four values or states. This allows a high level simulation in which physical devices are replaced by register transfer type operations. Data is altered and moved around using flow control mechanisms, logical and mathematical operations, and various means of specifying delay. Though not necessary or typical it is possible to model actual devices as ideal switches using these techniques. It is a multi-model simulation because simulation can occur at any level of design abstraction. Several examples are given including the modelling of the GR2 stack data microprocessor which was recently fabricated in NMOS.