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The impact of asynchrony on computer architecture

Manohar, Rajit (1998) The impact of asynchrony on computer architecture. California Institute of Technology , Pasadena, CA. (Unpublished)

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The performance characteristics of asynchronous circuits are quite different from those of their synchronous counterparts. As a result, the best asynchronous design of a particular system does not necessarily correspond to the best synchronous design, even at the algorithmic level. The goal of this thesis is to examine certain aspects of computer architecture and design in the context of an asynchronous VLSI implementation. We present necessary and sufficient conditions under which the degree of pipelining of a component can be modified without affecting the correctness of an asynchronous computation. As an instance of the improvements possible using an asynchronous architecture, we present circuits to solve the prefix problem with average-case behavior better than that possible by any synchronous solution in the case when the prefix operator has a right zero. We show that our circuit implementations are area-optimal given their performance characteristics, and have the best possible average-case latency. At the level of processor design, we present a mechanism for the implementation of precise exceptions in asynchronous processors. The novel feature of this mechanism is that it permits the presence of a data-dependent number of instructions in the execution pipeline of the processor. Finally, at the level of processor architecture, we present the architecture of a processor with an independent instruction stream for branches. The instruction set permits loops and function calls to be executed with minimal control-flow overhead.

Item Type:Report or Paper (Technical Report)
Additional Information:© 1998 California Institute of Technology. This research was supported by the Defence and Advanced Research Projects Agency under the office of Army Research and in part by a National Semiconductor Corporation graduate fellowship.
Group:Computer Science Technical Reports
Funding AgencyGrant Number
Defense Advanced Research Projects Agency (DARPA)UNSPECIFIED
National Semiconductor CorporationUNSPECIFIED
Army Research Office (ARO)UNSPECIFIED
Record Number:CaltechCSTR:1998.cs-tr-98-12
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Usage Policy:You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.
ID Code:27096
Deposited By: Imported from CaltechCSTR
Deposited On:06 Jun 2008
Last Modified:03 Oct 2019 03:20

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