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Hierarchical power routing

Johannsen, Dave (1978) Hierarchical power routing. Computer Science Technical Memorandum, 1978.2069. California Institute of Technology , Pasadena, CA. (Unpublished)

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Advances in LSI technology allow the system designer to implement large amounts of processing capability on a single silicon chip. It will soon be possible to construct a large number of processing elements on these chips. How will the system designer organize these processing elements? Hierarchically designed array or tree machines arc two possible alternatives. This paper provides a background for study of array and tree machines by examining how to supply power to an array of processing elements.

Item Type:Report or Paper (Technical Report)
Additional Information:Series numbering on title page: MEMO 2069
Group:Computer Science Technical Reports
Series Name:Computer Science Technical Memorandum
Issue or Number:1978.2069
Record Number:CaltechCSTR:1978.2069-tr-78
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Usage Policy:You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.
ID Code:27099
Deposited By: Imported from CaltechCSTR
Deposited On:18 Jul 2008
Last Modified:03 Oct 2019 03:20

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