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Bit-width Optimization for Configurable DSP’s by Multi-interval Analysis

Benedetti, A. and Perona, P. (2000) Bit-width Optimization for Configurable DSP’s by Multi-interval Analysis. In: Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems & Computers. Conference Record of the Asilomar Conference on Signals, Systems and Computers. IEEE , Piscataway, N.J., pp. 355-359. ISBN 0-7803-6514-3. https://resolver.caltech.edu/CaltechAUTHORS:20111123-082518994

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Abstract

A new algorithm for bounding the bit-widths of the data registers of an acyclic data-flow graph is presented. The method, based on the propagation of two's complement fixed-point numerical ranges, can be applied to both linear and nonlinear time invariant flow graphs and is well suited to be implemented in Field Programmable Gate Arrays (FPGA's). Numerical values are represented by unions of intervals, allowing automatic monitoring of the growth of the number of bits needed to represent the integer and the fractional part of intermediate variables. Central to this method is the definition of a new interval arithmetic on fixed point multi-intervals. An application of the proposed algorithm to the problem of detecting two dimensional visual features in video images is presented.


Item Type:Book Section
Related URLs:
URLURL TypeDescription
http://dx.doi.org/10.1109/ACSSC.2000.910977DOIUNSPECIFIED
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=910977&tag=1PublisherUNSPECIFIED
ORCID:
AuthorORCID
Perona, P.0000-0002-7583-5809
Additional Information:© 2000 IEEE. Date of Current Version: 06 August 2002.
Other Numbering System:
Other Numbering System NameOther Numbering System ID
INSPEC Accession Number7028160
Series Name:Conference Record of the Asilomar Conference on Signals, Systems and Computers
Record Number:CaltechAUTHORS:20111123-082518994
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:20111123-082518994
Official Citation:Benedetti, A.; Perona, P.; , "Bit-width optimization for configurable DSP's by multi-interval analysis," Signals, Systems and Computers, 2000. Conference Record of the Thirty-Fourth Asilomar Conference on , vol.1, no., pp.355-359 vol.1, 2000 doi: 10.1109/ACSSC.2000.910977 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=910977&isnumber=19646
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:27936
Collection:CaltechAUTHORS
Deposited By: Ruth Sustaita
Deposited On:23 Nov 2011 16:41
Last Modified:03 Oct 2019 03:27

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