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Delay-insensitive pipelined communication on parallel buses

Blaum, Mario and Bruck, Jehoshua (1995) Delay-insensitive pipelined communication on parallel buses. IEEE Transactions on Computers, 44 (5). pp. 660-668. ISSN 0018-9340. doi:10.1109/12.381951. https://resolver.caltech.edu/CaltechAUTHORS:20120215-131718595

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Abstract

Consider a communication channel that consists of several subchannels transmitting simultaneously and asynchronously. As an example of this scheme, we can consider a board with several chips. The subchannels represent wires connecting between the chips where differences in the lengths of the wires might result in asynchronous reception. In current technology, the receiver acknowledges reception of the message before the transmitter sends the following message. Namely, pipelined utilization of the channel is not possible. Our main contribution is a scheme that enables transmission without an acknowledgment of the message, therefore enabling pipelined communication and providing a higher bandwidth. However, our scheme allows for a certain number of transitions from a second message to arrive before reception of the current message has been completed, a condition that we call skew. We have derived necessary and sufficient conditions for codes that can tolerate a certain amount of skew among adjacent messages (therefore, allowing for continuous operation) and detect a larger amount of skew when the original skew is exceeded. These results generalize previously known results. We have constructed codes that satisfy the necessary and sufficient conditions, studied their optimality, and devised efficient decoding algorithms. To the best of our knowledge, this is the first known scheme that permits efficient asynchronous communications without acknowledgment. Potential applications are in on-chip, on-board, and board to board communications, enabling much higher communication bandwidth.


Item Type:Article
Related URLs:
URLURL TypeDescription
http://dx.doi.org/10.1109/12.381951 DOIUNSPECIFIED
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=381951PublisherUNSPECIFIED
ORCID:
AuthorORCID
Bruck, Jehoshua0000-0001-8474-0812
Additional Information:© 1995 IEEE. Manuscript received Apr. 8, 1993. We are grateful to one of the referees whose comments helped in improving the precision of the presentation.
Other Numbering System:
Other Numbering System NameOther Numbering System ID
INSPEC Accession Number4969399
Issue or Number:5
DOI:10.1109/12.381951
Record Number:CaltechAUTHORS:20120215-131718595
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:20120215-131718595
Official Citation:Blaum, M.; Bruck, J.; , "Delay-insensitive pipelined communication on parallel buses," Computers, IEEE Transactions on , vol.44, no.5, pp.660-668, May 1995 doi: 10.1109/12.381951 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=381951&isnumber=8654
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:29306
Collection:CaltechAUTHORS
Deposited By: Tony Diaz
Deposited On:20 Mar 2012 22:58
Last Modified:09 Nov 2021 17:05

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