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A 3x9 Gb/s Shared, All-Digital CDR for High-Speed, High-Density I/O

Loh, Matthew and Emami-Neyestanak, Azita (2012) A 3x9 Gb/s Shared, All-Digital CDR for High-Speed, High-Density I/O. IEEE Journal of Solid-State Circuits, 47 (3). pp. 641-651. ISSN 0018-9200. doi:10.1109/JSSC.2011.2178557. https://resolver.caltech.edu/CaltechAUTHORS:20120320-133331713

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Abstract

This paper presents a novel all-digital CDR scheme in 90 nm CMOS. Two independently adjustable clock phases are generated from a delay line calibrated to 2 UI. One clock phase is placed in the middle of the eye to recover the data (“data clock”) and the other is swept across the delay line (“search clock”). As the search clock is swept, its samples are compared against the data samples to generate eye information. This information is used to determine the best phase for data recovery. After placing the search clock at this phase, search and data functions are traded between clocks and eye monitoring repeats. By trading functions, infinite delay range is realized using only a calibrated delay line, instead of a PLL or DLL. Since each clock generates its own alignment information, mismatches in clock distribution can be tolerated. The scheme's generalized sampling and retiming architecture is used in an efficient sharing technique that reduces the number of clocks required, saving power and area in high-density interconnect. The shared CDR is implemented using static CMOS logic in a 90 nm bulk process, occupying 0.15 mm^2. It operates from 6 to 9 Gb/s, and consumes 2.5 mW/Gb/s of power at 6 Gb/s and 3.8 mW/Gb/s at 9 Gb/s.


Item Type:Article
Related URLs:
URLURL TypeDescription
http://dx.doi.org/10.1109/JSSC.2011.2178557 DOIUNSPECIFIED
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6132382&tag=1PublisherUNSPECIFIED
ORCID:
AuthorORCID
Emami-Neyestanak, Azita0000-0003-2608-9691
Additional Information:© 2012 IEEE. Manuscript received June 02, 2011; revised October 17, 2011; accepted November 10, 2011. Date of publication January 16, 2012; date of current version February 23, 2012. This paper was approved by Associate Editor Jared Zerbe. This work was supported by the National Science Foundation, Intel, and the C2S2 Focus Center, funded under the Focus Center Research Program (FCRP), a Semiconductor Research Corporation subsidiary. The authors acknowledge the contributions of J. Yoo for helpful technical discussions, H. Mani for advice in the fabrication of the test board, and the funding support of NSF, Intel and the C2S2 Focus Center.
Funders:
Funding AgencyGrant Number
NSFUNSPECIFIED
IntelUNSPECIFIED
Focus Center Research Program (FCRP) C2S2 Focus CenterUNSPECIFIED
Subject Keywords:All-digital CDR; calibrated delay line; clock and data recovery (CDR); eye-monitor; parallel link; per-pin synchronization; shared CDR; static CMOS logic
Other Numbering System:
Other Numbering System NameOther Numbering System ID
INSPEC Accession Number12543296
Issue or Number:3
DOI:10.1109/JSSC.2011.2178557
Record Number:CaltechAUTHORS:20120320-133331713
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:20120320-133331713
Official Citation:Loh, M.; Emami-Neyestanak, A.; , "A 3x9 Gb/s Shared, All-Digital CDR for High-Speed, High-Density I/O," Solid-State Circuits, IEEE Journal of , vol.47, no.3, pp.641-651, March 2012 doi: 10.1109/JSSC.2011.2178557 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6132382&isnumber=6155198
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:29786
Collection:CaltechAUTHORS
Deposited By: Tony Diaz
Deposited On:20 Mar 2012 21:22
Last Modified:09 Nov 2021 19:29

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