A Caltech Library Service

VLSI Architecture and Design

Johnsson, Lennart (1980) VLSI Architecture and Design. Computer Science Technical Memorandum, 1980.3857. California Institute of Technology , Pasadena, CA. (Unpublished)

PDF - Submitted Version
See Usage Policy.


Use this Persistent URL to link to this item:


Integrated circuit technology is rapidly approaching a state where feature sizes of one micron or less are tractable. Chip sizes are increasing slowly. These two developments result in considerably increased complexity in chip design. The physical characteristics of integrated circuit technology are also changing. The cost of communication will be dominating making new architectures and algorithms both feasible and desirable. A large number of processors on a single chip will be possible. The cost of communication will make designs enforcing locality superior to other types of designs. Scaling down feature sizes results in increase of the delay that wires introduce. The delay even of metal wires will become significant. Time tends to be a local property which will make the design of globally synchronous systems more difficult. Self-timed systems will eventually become a necessity. With the chip complexity measured in terms of logic devices increasing by more than an order of magnitude over the next few years the importance of efficient design methodologies and tools become crucial. Hierarchical and structured design are ways of dealing with the complexity of chip design. Structered design focuses on the information flow and enforces a high degree of regularity. Both hierarchical and structured design encourage the use of cell libraries. The geometry of the cells in such libraries should be parameterized so that for instance cells can adjust there size to neighboring cells and make the proper interconnection. Cells with this quality can be used as a basis for "Silicon Compilers".

Item Type:Report or Paper (Technical Report)
Additional Information:Presented at National Electronics Conference Chicago, Illinois, October, 1980. The research described in this paper was sponsored by the Defense Advanced Research Projects Agency, ARPA Order number 3771, and monitored by the Office of Naval Research under contract number N00014-79-C-0597
Group:Computer Science Technical Reports
Funding AgencyGrant Number
Defense Advanced Research Projects Agency (DARPA)3771
Office of Naval Research (ONR)N00014-79-C-0597
Series Name:Computer Science Technical Memorandum
Issue or Number:1980.3857
Record Number:CaltechAUTHORS:20120418-110634950
Persistent URL:
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:30164
Deposited On:18 Apr 2012 18:39
Last Modified:03 Oct 2019 03:48

Repository Staff Only: item control page