Mead, Carver and Rem, Martin (1983) Minimum propagation delays in VLSI. California Institute of Technology , Pasadena, CA. (Unpublished) https://resolver.caltech.edu/CaltechAUTHORS:20120420-104637505
![[img]](https://authors.library.caltech.edu/style/images/fileicons/application_pdf.png)
|
PDF
See Usage Policy. 1MB |
Use this Persistent URL to link to this item: https://resolver.caltech.edu/CaltechAUTHORS:20120420-104637505
Abstract
In this paper we demonstrate that it is possible to achieve propagation delays that are logarithmic in the lengths of the wires, provided the connection pattern is designed to meet rather strong constraints. These constraints are, in effect, satisfied only by connection patterns that exhibit a hierarchical structure. We also show that, even at the ultimate physical limits of the technology, the propagation for reasonably sized VLSI chips is dominated by these considerations, rather than by the speed of light.
| Item Type: | Report or Paper (Technical Report) | ||||||
|---|---|---|---|---|---|---|---|
| Additional Information: | Copyright, California Institute of Technology, 1981. The research described in this paper was sponsored by the Office of Naval Research Contract No. N00014-76-C-0367 and by the Defense Advanced Research Agency, ARPA Order number 3771, and monitored by the Office of Naval Research under Contract number N00014-79-C-0597. | ||||||
| Group: | Computer Science Technical Reports | ||||||
| Funders: |
| ||||||
| Other Numbering System: |
| ||||||
| Record Number: | CaltechAUTHORS:20120420-104637505 | ||||||
| Persistent URL: | https://resolver.caltech.edu/CaltechAUTHORS:20120420-104637505 | ||||||
| Usage Policy: | No commercial reproduction, distribution, display or performance rights in this work are provided. | ||||||
| ID Code: | 30220 | ||||||
| Collection: | CaltechCSTR | ||||||
| Deposited By: | INVALID USER | ||||||
| Deposited On: | 02 May 2012 17:51 | ||||||
| Last Modified: | 03 Oct 2019 03:48 |
Repository Staff Only: item control page
