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Concurrent fault simulation of MOS digital circuits

Schuster, Michael D. and Bryant, Randal E. (1983) Concurrent fault simulation of MOS digital circuits. California Institute of Technology , Pasadena, CA. (Submitted)

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The concurrent fault simulation technique is widely used to analyse the behavior of digital circuits in the presence of faults. We show how this technique can be applied to metal-oxide-semiconductor (MOS) digital circuits when modeled at the switch-level as a set of charge storage nodes connected by bidirectional transistor switches. The algorithm we present is capable of analysing the behavior of a wide variety of MOS circuit failures, such as stuck-at-zero or stuck-at-one nodes, stuck-open or stuck-closed transistors, or resistive opens or shorts. We have implemented a fault simulator FMOSSIM based on this algorithm. The capabilities and the peformance of this program demonstrate the advantages of combining switch-level and concurrent simulation techniques.

Item Type:Report or Paper (Technical Report)
Additional Information:© Artech House, 1984. To be presented at the Conference on Advanced Research in VLSI, to be held at the Massachusetts Institute of Technology, January 1984. Proceedings published by Artech House, Inc:., Dedham, MA 02026. This research was supported in part by the IBM Corporation and by the Defense Advanced Research Contracts Agency, ARPA Order 3771. Michael Schuster was supported in part by a Bell Laboratories Ph.D. Scholarship.
Group:Computer Science Technical Reports
Funding AgencyGrant Number
Defense Advanced Research Projects Agency (DARPA)ARPA order 3771
Bell LaboratoriesUNSPECIFIED
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Other Numbering System NameOther Numbering System ID
Computer Science Technical Memorandum5101
Record Number:CaltechAUTHORS:20120420-114600956
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Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:30231
Deposited On:02 May 2012 17:45
Last Modified:03 Oct 2019 03:48

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