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Chip assembly tools

Trimberger, Stephen and Kingsley, Chris (1982) Chip assembly tools. California Institute of Technology , Pasadena, CA. (Unpublished)

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In large-scale integrated circuit design, chip assembly is more difficult, more time consuming. and more error prone than the design of the low-level cells. Assembly errors tend to persist until late in the design cycle requiring extensive rework. Unfortunately, the tools traditionally provided for custom integrated circuit design address the problems of cell design well, but do not properly address the problems of chip assembly. A great deal of emphasis at Caltech has been placed on tools that do address chip assembly. This paper reports on some of these tools.

Item Type:Report or Paper (Technical Report)
Additional Information:We would like to thank those people at Caltech who have allowed us to report on their work, notably Dave Johannsen, for Bristle Blocks; and John Tanner, the author of Comped. The work reported in this paper was supported by the Caltech Silicon Structures Project and by the United States Department of Defense Advanced Research Projects Agency.
Group:Computer Science Technical Reports
Funding AgencyGrant Number
Caltech Silicon Structures ProjectUNSPECIFIED
Defense Advanced Research Projects Agency (DARPA)UNSPECIFIED
Other Numbering System:
Other Numbering System NameOther Numbering System ID
Computer Science Technical Memorandum5005
Record Number:CaltechAUTHORS:20120423-105037951
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Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:30254
Deposited On:23 Apr 2012 21:13
Last Modified:03 Oct 2019 03:48

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