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High-density IC chip integration with parylene pocket

Chang, Jay Han-Chieh and Huang, Ray and Tai, Yu-Chong (2011) High-density IC chip integration with parylene pocket. In: Proceedings of the 6th IEEE International Conference on Nano/Micro Engineered and Molecular Systems. IEEE , Piscataway, NJ, pp. 1067-1070. ISBN 978-1-61284-775-7.

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We utilize the parylene pocket technology and develop a novel integration scheme that will allow us to connect more than 100 bonding pads on an area less than 5 mm × 5 mm with high efficiency. This packaging technique can also house any IC chip or discrete component and provide electrical connection to it. Here we use squeegee technique to connect each pad on the chip with the bonding pad on the pocket to achieve functionality because the chip that is to be integrated in this section has a very dense array and it is impractical and extremely difficult to connect everything manually. Devices testing are done by testing dummy chip integration and soaking test. Positive results prove that such parylene pocket packaging technique works well.

Item Type:Book Section
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Tai, Yu-Chong0000-0001-8529-106X
Additional Information:© 2011 IEEE. Date of Current Version: 12 September 2011. The authors would like to thank our lab manager, Trevor Roper, for his technical assistance in terms of device fabrication and our group members for fruitful discussions.
Subject Keywords:parylene pocket; packaging; squeegee; soaking test
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INSPEC Accession Number12229794
Record Number:CaltechAUTHORS:20121105-083903340
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Official Citation:Chang, J.H.-C.; Huang, R.; Yu-Chong Tai; , "High-density IC chip integration with parylene pocket," Nano/Micro Engineered and Molecular Systems (NEMS), 2011 IEEE International Conference on , vol., no., pp.1067-1070, 20-23 Feb. 2011 doi: 10.1109/NEMS.2011.6017541 URL:
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:35275
Deposited By: Tony Diaz
Deposited On:14 Nov 2012 19:26
Last Modified:03 Oct 2019 04:26

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