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Three-dimensional etching of silicon for the fabrication of low-dimensional and suspended devices

Walavalkar, Sameer S. and Homyk, Andrew P. and Henry, M. David and Scherer, Axel (2012) Three-dimensional etching of silicon for the fabrication of low-dimensional and suspended devices. Nanoscale, 5 (3). pp. 927-931. ISSN 2040-3372.

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In order to expand the use of nanoscaled silicon structures we present a new etching method that allows us to shape silicon with sub-10 nm precision. This top-down, CMOS compatible etching scheme allows us to fabricate silicon devices with quantum behavior without relying on difficult lateral lithography. We utilize this novel etching process to create quantum dots, quantum wires, vertical transistors and ultra-high-aspect ratio structures. We believe that this etching technique will have broad and significant impacts and applications in nano-photonics, bio-sensing, and nano-electronics.

Item Type:Article
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Walavalkar, Sameer S.0000-0002-7628-9600
Henry, M. David0000-0002-5201-0644
Additional Information:© 2013 The Royal Society of Chemistry. Received 28th September 2012; Accepted 11th December 2012. First published on the web 13 Dec 2012. This work was supported by the Advanced Energy Commission under the BEG10-07 grant, the Boeing corporation under the CT-BA-GTA-1 grant, and by the National Science Foundation under NSF CIAN ERC (EEC-0812072). S.W. would like to thank T.K. Nelson for useful discussion and A.H. appreciates the generous support of the ARCS Foundation. The authors would like to additionally thank the staff of the Kavli Nanoscience Institute for their continued help.
Group:Kavli Nanoscience Institute
Funding AgencyGrant Number
Advanced Energy ConsortiumBEG10-07
Boeing CorporationCT-BA-GTA-1
Issue or Number:3
Record Number:CaltechAUTHORS:20130221-152750562
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Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:37059
Deposited By: Tony Diaz
Deposited On:22 Feb 2013 23:44
Last Modified:03 Oct 2019 04:44

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