Sarpeshkar, Rahul and Wattanapanitch, Woradorn and Arfin, Scott K. and Rapoport, Benjamin I. and Mandal, Soumyajit and Baker, Michael W. and Fee, Michale S. and Musallam, Sam and Andersen, Richard A. (2008) Low-Power Circuits for Brain–Machine Interfaces. IEEE Transactions on Biomedical Circuits and Systems, 2 (3). pp. 173-183. ISSN 1932-4545. doi:10.1109/TBCAS.2008.2003198. https://resolver.caltech.edu/CaltechAUTHORS:20130304-154929601
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Abstract
This paper presents work on ultra-low-power circuits for brain–machine interfaces with applications for paralysis prosthetics, stroke, Parkinson’s disease, epilepsy, prosthetics for the blind, and experimental neuroscience systems. The circuits include a micropower neural amplifier with adaptive power biasing for use in multi-electrode arrays; an analog linear decoding and learning architecture for data compression; low-power radio-frequency (RF) impedance-modulation circuits for data telemetry that minimize power consumption of implanted systems in the body; a wireless link for efficient power transfer; mixed-signal system integration for efficiency, robustness, and programmability; and circuits for wireless stimulation of neurons with power-conserving sleep modes and awake modes. Experimental results from chips that have stimulated and recorded from neurons in the zebra finch brain and results from RF power-link, RF data-link, electrode- recording and electrode-stimulating systems are presented. Simulations of analog learning circuits that have successfully decoded prerecorded neural signals from a monkey brain are also presented.
| Item Type: | Article | |||||||||
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| Additional Information: | © 2008 IEEE. Manuscript received November 01, 2007; revised May 16, 2008. Current version published October 24, 2008. This work was supported in part by a grant from the McGovern Institute Neurotechnology Program (MINT) at MIT. This paper was recommended by Associate Editor M. Sawan. | |||||||||
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| Subject Keywords: | Brain–machine interfaces; low-power; prosthetics; wireless neuroscience | |||||||||
| Issue or Number: | 3 | |||||||||
| DOI: | 10.1109/TBCAS.2008.2003198 | |||||||||
| Record Number: | CaltechAUTHORS:20130304-154929601 | |||||||||
| Persistent URL: | https://resolver.caltech.edu/CaltechAUTHORS:20130304-154929601 | |||||||||
| Official Citation: | Sarpeshkar, R.; Wattanapanitch, W.; Arfin, S.K.; Rapoport, B.I.; Mandal, S.; Baker, M.W.; Fee, M.S.; Musallam, S.; Andersen, R.A., "Low-Power Circuits for Brain–Machine Interfaces," Biomedical Circuits and Systems, IEEE Transactions on , vol.2, no.3, pp.173,183, Sept. 2008 | |||||||||
| Usage Policy: | No commercial reproduction, distribution, display or performance rights in this work are provided. | |||||||||
| ID Code: | 37283 | |||||||||
| Collection: | CaltechAUTHORS | |||||||||
| Deposited By: | Tony Diaz | |||||||||
| Deposited On: | 06 Mar 2013 23:18 | |||||||||
| Last Modified: | 09 Nov 2021 23:28 |
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