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Reconfigurable Processor for Energy-Efficient Computational Photography

Rithe, Rahul and Raina, Priyanka and Ickes, Nathan and Tenneti, Srikanth V. and Chandrakasan, Anantha P. (2013) Reconfigurable Processor for Energy-Efficient Computational Photography. IEEE Journal of Solid-State Circuits, 48 (11). pp. 2908-2919. ISSN 0018-9200. https://resolver.caltech.edu/CaltechAUTHORS:20131203-093142440

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Abstract

This paper presents an on-chip implementation of a scalable reconfigurable bilateral filtering processor for computational photography applications such as HDR imaging, low-light enhancement, and glare reduction. Careful pipelining and scheduling has minimized the local storage requirement to tens of kB. The 40-nm CMOS test chip operates from 98 MHz at 0.9 V to 25 MHz at 0.5 V. The test chip processes 13 megapixels/s while consuming 17.8 mW at 98 MHz and 0.9 V, achieving significant energy reduction compared with software implementations on recent mobile processors.


Item Type:Article
Related URLs:
URLURL TypeDescription
http://dx.doi.org/10.1109/JSSC.2013.2282614DOIArticle
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6623206PublisherArticle
http://dx.doi.org/10.1109/JSSC.2014.2353797 ErrataCorrection
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6899696ErrataCorrection
ORCID:
AuthorORCID
Tenneti, Srikanth V.0000-0002-5415-3681
Additional Information:© 2013 IEEE. Manuscript received June 03, 2013; accepted August 06, 2013. Date of publication October 07, 2013; date of current version October 19, 2013. This paper was approved by Associate Editor Stefan Rusu. This work was supported by the Foxconn Technology Group. The authors would like to thank the TSMC University Shuttle Program for chip fabrication and Prof. F. Durand and J. Regan-Kelley for valuable feedback and suggestions.
Funders:
Funding AgencyGrant Number
Foxconn Technology GroupUNSPECIFIED
Subject Keywords:Bilateral filtering, bilateral grid, computational photography, high-dynamic-range (HDR) imaging, low-power electronics, low-voltage operation, voltage scaling.
Other Numbering System:
Other Numbering System NameOther Numbering System ID
INSPEC Accession Number13852163
Issue or Number:11
Record Number:CaltechAUTHORS:20131203-093142440
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:20131203-093142440
Official Citation:Rithe, R.; Raina, P.; Ickes, N.; Tenneti, S.V.; Chandrakasan, A.P., "Reconfigurable Processor for Energy-Efficient Computational Photography," Solid-State Circuits, IEEE Journal of , vol.48, no.11, pp.2908,2919, Nov. 2013 doi: 10.1109/JSSC.2013.2282614
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:42791
Collection:CaltechAUTHORS
Deposited By: Ruth Sustaita
Deposited On:03 Dec 2013 18:01
Last Modified:09 Mar 2020 13:19

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