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Constrained Codes that Mitigate Inter-Cell Interference in Read/Write Cycles for Flash Memories

Qin, Minghai and Yaakobi, Eitan and Siegel, Paul H. (2014) Constrained Codes that Mitigate Inter-Cell Interference in Read/Write Cycles for Flash Memories. IEEE Journal on Selected Areas in Communications, 32 (5). pp. 836-846. ISSN 0733-8716. http://resolver.caltech.edu/CaltechAUTHORS:20140603-141727280

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Abstract

Inter-cell interference (ICI) is one of the main obstacles to precise programming (i.e., writing) of a flash memory. In the presence of ICI, the voltage level of a cell might increase unexpectedly if its neighboring cells are programmed to high levels. For q-ary cells, the most severe ICI arises when three consecutive cells are programmed to levels high - low - high, represented as (q-1)0(q-1), resulting in an unintended increase in the level of the middle cell and the possibility of decoding it incorrectly as a nonzero value. ICI-free codes are used to mitigate this phenomenon by preventing the programming of any three consecutive cells as (q-1)0(q-1). In this work, we extend ICI-free codes in two directions. First, we consider binary balanced ICI-free codes which, in addition to forbidding the 101 pattern, require the number of 0 symbols and 1 symbols to be the same. Using combinatorial methods, we determine the asymptotic information rate of these codes and show that the asymptotic rate loss due to the imposition of the balanced property is approximately 2%. Extensions to q-ary cells, for q>2 are also discussed. Next, we consider q-ary ICI-free write-once-memory (WOM) codes that support multiple writes of a WOM while mitigating ICI effects. These codes forbid the appearance of the (q-1)0(q-1) pattern in any codeword used in any writing step. Using properties of two-dimensional constrained codes and generalized WOMs, we characterize the maximum sum-rate of t-write ICI-free WOM codes or, equivalently, the t-write sum-capacity of an ICI-free WOM.


Item Type:Article
Related URLs:
URLURL TypeDescription
http://dx.doi.org/10.1109/JSAC.2014.140504DOIArticle
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6804929PublisherArticle
Additional Information:© 2014 IEEE. Date of Current Version: 24 April 2014. Manuscript received May 15, 2013; revised October 1, 2013 and December 10, 2013. This research was supported in part by the ISEF Foundation, the Lester Deutsch Fellowship, the University of California Lab Fees Research Program, Award No. 09-LR-06-118620-SIEP, the National Science Foundation under Grant CCF-1116739, and the Center for Magnetic Recording Research at the University of California, San Diego. The authors would like to thank David Callan for the proof of Equation (1) and would like to thank Aman Bhatia, Ryan Gabrys, and Anxiao Jiang for helpful discussions.
Funders:
Funding AgencyGrant Number
ISEF FoundationUNSPECIFIED
Lester Deutsch FellowshipUNSPECIFIED
University of California Lab Fees Research Program, Award09-LR-06-118620-SIEP
NSFCCF-1116739
University of California, San Diego Center for Magnetic Recording ResearchUNSPECIFIED
Subject Keywords:Constrained codes, flash memories, write-once memories
Record Number:CaltechAUTHORS:20140603-141727280
Persistent URL:http://resolver.caltech.edu/CaltechAUTHORS:20140603-141727280
Official Citation:Qin, Minghai; Yaakobi, Eitan; Siegel, Paul H., "Constrained Codes that Mitigate Inter-Cell Interference in Read/Write Cycles for Flash Memories," Selected Areas in Communications, IEEE Journal on , vol.32, no.5, pp.836,846, May 2014 doi: 10.1109/JSAC.2014.140504
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:46055
Collection:CaltechAUTHORS
Deposited By: Ruth Sustaita
Deposited On:03 Jun 2014 21:45
Last Modified:03 Jun 2014 21:45

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