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Tertiary-Tree 12-GHz 32-bit Adder in 65nm Technology

Agah, Amir and Fakhraie, S. Mehdi and Emami-Neyestanak, Azita (2007) Tertiary-Tree 12-GHz 32-bit Adder in 65nm Technology. In: IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007. IEEE , Piscataway, NJ, pp. 3006-3009. ISBN 1-4244-0920-9.

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This paper presents a new 32-bit adder structure with 12 GHz low-power operation in 65nm technology. The Fast Conditional Sparse-Tree Logic (FCSL) is based on modifying the initial Sparse-Tree architecture [1] to enhance its speed using tertiary trees and applying a carry-select scheme in some of the more significant bits. This design has been compared with the Sparse-Tree adder and the Low-Voltage Swing adder in terms of speed and power. It has been shown that speed can be improved using FCSL architecture while keeping the power at a comparable level.

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Emami-Neyestanak, Azita0000-0003-2608-9691
Additional Information:©2007 IEEE.
Record Number:CaltechAUTHORS:20140609-103233137
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Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:46147
Deposited By: Kristin Buxton
Deposited On:09 Jun 2014 18:25
Last Modified:03 Oct 2019 06:41

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