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How tunneling currents reduce plasma-induced charging

Hwang, Gyeong S. and Giapis, Konstantinos P. (1997) How tunneling currents reduce plasma-induced charging. Applied Physics Letters, 71 (20). pp. 2928-2930. ISSN 0003-6951. doi:10.1063/1.120218.

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As semiconductor manufacturing moves towards smaller logic devices and thinner gate oxides, there is serious concern that pattern-dependent charging during plasma etching will impede progress by distorting etch profiles and by causing oxide breakdown. Simulations of the final overetch predict that the use of ultrathin oxides (<= 5 nm), combined with a low substrate potential, will actually eliminate notching by enabling electron tunneling from the substrate to decrease surface charging potentials at the bottom of high aspect ratio trenches. Comparison with published experimental results validates the simulations.

Item Type:Article
Related URLs:
URLURL TypeDescription
Hwang, Gyeong S.0000-0002-5538-9426
Giapis, Konstantinos P.0000-0002-7393-298X
Additional Information:© 1997 American Institute of Physics. (Received 24 June 1997; accepted 18 September 1997) This work was supported by an NSF-Career Award and a Camille Dreyfus Teacher-Scholar Award to KPG.
Funding AgencyGrant Number
Camille and Henry Dreyfus FoundationUNSPECIFIED
Subject Keywords:sputter etching; surface charging; tunnelling; semiconductor technology
Issue or Number:20
Record Number:CaltechAUTHORS:HWAapl97a
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Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:4806
Deposited By: Archive Administrator
Deposited On:07 Sep 2006
Last Modified:08 Nov 2021 20:20

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