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An 18.6Gb/s double-sampling receiver in 65nm CMOS for ultra-low-power optical communication

Nazari, Meisam Honarvar and Emami-Neyestanak, Azita (2012) An 18.6Gb/s double-sampling receiver in 65nm CMOS for ultra-low-power optical communication. In: 2012 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC). IEEE , Piscataway, NJ, pp. 130-131. ISBN 978-1-4673-0376-7. https://resolver.caltech.edu/CaltechAUTHORS:20140820-151052084

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Abstract

Using optics for chip-to-chip interconnects has recently gained a lot of interest. As data rates scale to meet increasing bandwidth requirements, the shortcomings of copper channels are becoming more severe. Hybrid integration of optical devices with electronics has been demonstrated to achieve high performance, and recent advances in silicon photonics have led to fully integrated optical signaling. These approaches pave the way to massively parallel optical communications. Dense arrays of optical detectors require very low-power, sensitive, and compact optical receiver circuits. Existing designs for the input receiver, such as TIA, require large power consumption to achieve high band width and low noise, and can occupy large area due to bandwidth-enhancement inductors. In this work, a compact low-power optical receiver that scales well with technology is designed to explore the potential of optical signaling for future chip-to-chip and on-chip communication.


Item Type:Book Section
Related URLs:
URLURL TypeDescription
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6176949PublisherChapter
http://dx.doi.org/10.1109/ISSCC.2012.6176949DOIChapter
ORCID:
AuthorORCID
Emami-Neyestanak, Azita0000-0003-2608-9691
Additional Information:©2012 IEEE. The authors acknowledge the support of NSF, FCRP, Cosemi Tech Inc, and STMicroelectronics. M. Nazari would like to thank Z. Safarian for constant help and support.
Funders:
Funding AgencyGrant Number
NSFUNSPECIFIED
FCRPUNSPECIFIED
Cosemi TechUNSPECIFIED
STMicroelectronicsUNSPECIFIED
DOI:10.1109/ISSCC.2012.6176949
Record Number:CaltechAUTHORS:20140820-151052084
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:20140820-151052084
Official Citation:Nazari, M.H.; Emami-Neyestanak, A, "An 18.6Gb/s double-sampling receiver in 65nm CMOS for ultra-low-power optical communication," Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International , vol., no., pp.130,131, 19-23 Feb. 2012 doi: 10.1109/ISSCC.2012.6176949
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:48745
Collection:CaltechAUTHORS
Deposited By: Kristin Buxton
Deposited On:20 Aug 2014 22:24
Last Modified:10 Nov 2021 18:35

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