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VLSI architectures for implementation of neural networks

Sivilotti, Massimo A. and Emerling, Michael R. and Mead, Carver A. (1986) VLSI architectures for implementation of neural networks. In: Neural Networks for Computing. AIP Conference Proceedings. No.151. American Institute of Physics , Melville, NY, pp. 408-413. ISBN 0-88318-351-X.

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A large scale collective system implementing a specific model for associative memory was described by Hopfield [1]. A circuit model for this operation is illustrated in Figure 1, and consists of three major components. A collection of active gain elements (called amplifiers or "neurons") with gain function V = g(v) are connected by a passive interconnect matrix which provides unidirectional excitatory or inhibitory connections ("synapses") between the output of one neuron and the input to another. The strength of this interconnection is given by the conductance G_(ij) = G_0T_(ij). The requirements placed on the gain function g(v) are not very severe [2], and easily met by VLSI-realizable amplifiers. The third circuit element is the capacitances that determine the time evolution of the system, and are modelled as lumped capacitances. This formulation leads to the equations of motion shown in Figure 2, and to a Liapunov energy function which determines the dynamics of the system, and predicts the location of stable states (memories) in the case of a symmetric matrix T.

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Additional Information:© 1986 American Institute of Physics. This research was supported by the System Development Foundation.
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Series Name:AIP Conference Proceedings
Issue or Number:151
Record Number:CaltechAUTHORS:20141215-164438997
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ID Code:52838
Deposited On:16 Dec 2014 17:38
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