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Analog VLSI model of binaural hearing

Mead, Carver A. and Arreguit, Xavier and Lazzaro, John (1991) Analog VLSI model of binaural hearing. IEEE Transactions on Neural Networks, 2 (2). pp. 230-236. ISSN 1045-9227. doi:10.1109/72.80333.

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The stereausis model of biological auditory processing was proposed as a representation that encodes both binaural and spectral information in a unified framework. We describe a working analog VLSI chip that implements this model of early auditory processing in the brain. The chip is a 100 000-transistor integrated circuit that computes the stereausis representation in real time, using continuous-time analog processing. The chip receives two audio inputs, representing sound entering the two ears, computes the stereausis representation, and generates output signals that can directly drive a color CRT display.

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Additional Information:© Copyright 1991 IEEE. Manuscript received August 21, 1990; rev:sed Novernher 22, 1990. This work was supported by the Office of Naval Research, the California Office of Competitive Technology, and the System Development Foundation. IEEE Log Number 9042028. The authors thank R. Lyon for many helpful discussions. Chip fabrication was provided by DARPA through the MOSIS fabrication service.
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Office of Naval Research (ONR)UNSPECIFIED
California Office of Competitive TechnologyUNSPECIFIED
System Development FoundationUNSPECIFIED
Issue or Number:2
Record Number:CaltechAUTHORS:20141222-115251890
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Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:53091
Deposited On:22 Dec 2014 20:03
Last Modified:10 Nov 2021 19:47

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