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Scaling of MOS Technology to Submicrometer Feature Sizes

Mead, Carver A. (1994) Scaling of MOS Technology to Submicrometer Feature Sizes. Analog Integrated Circuits and Signal Processing, 6 (1). pp. 9-25. ISSN 0925-1030. https://resolver.caltech.edu/CaltechAUTHORS:20141222-161742429

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Abstract

Industries based on MOS technology now play a prominent role in the developed and the developing world. More importantly, MOS technology drives a large proportion of innovation in many technologies. It is likely that the course of technological development depends more on the capability of MOS technology than on any other technical factor. Therefore, it is worthwhile investigating the nature and limits of future improvements to MOS fabrication. The key to improved MOS technology is reduction in feature size. Reduction in feature size, and the attendant changes in device behavior, will shape the nature of effective uses of the technology at the system level. This paper reviews recent, and historical, data on feature scaling and device behavior, and attempts to predict the limits to this scaling. We conclude with some remarks on the system-level implications of feature size as the minimum size approaches physical limits.


Item Type:Article
Related URLs:
URLURL TypeDescription
http://dx.doi.org/10.1007/BF01250732DOIArticle
http://link.springer.com/article/10.1007%2FBF01250732PublisherArticle
Additional Information:© 1994 Kluwer Academic Publishers. Received June 8, 1993; Revised July 27, 1993.
Issue or Number:1
Record Number:CaltechAUTHORS:20141222-161742429
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:20141222-161742429
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:53122
Collection:CaltechAUTHORS
Deposited By: Kristin Buxton
Deposited On:23 Dec 2014 16:42
Last Modified:03 Oct 2019 07:47

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