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Scaling of MOS Technology to Submicrometer Feature Sizes

Mead, Carver A. (1999) Scaling of MOS Technology to Submicrometer Feature Sizes. In: Feynman and computation : exploring the limits of computers. Perseus Books , Reading, MA, pp. 93-115. ISBN 0738200573. https://resolver.caltech.edu/CaltechAUTHORS:20150109-120856432

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Abstract

Industries based on MOS technology now play a prominent role in the developed and the developing world. More importantly, MOS technology drives a large proportion of innovation in many technologies. It is likely that the course of technological development depends more on the capability of MOS technology than on any other technical factor. Therefore, it is worthwhile investigating the nature and limits of future improvements to MOS fabrication. The key to improved MOS technology is reduction in feature size. Reduction in feature size, and the attendant changes in device behaviour, will shape the nature of effective uses of the technology at the system level. This paper reviews recent, and historical, data on feature scaling and device behavior, and attempts to predict the limits to this scaling. We conclude with some remarks on the system-level implications of feature size as the minimum size approaches physical limits.


Item Type:Book Section
Additional Information:© 1999 Perseus Books. Reproduced from Journal of VLSI Signal Processing, 8, 9-25 (1994) Kluwer Academic Publishers, Boston. Manufactured in The Netherlands.
Record Number:CaltechAUTHORS:20150109-120856432
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:20150109-120856432
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:53483
Collection:CaltechAUTHORS
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Deposited On:09 Jan 2015 23:02
Last Modified:03 Oct 2019 07:50

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