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A Low-Power Wide-Dynamic-Range Analog VLSI Cochlea

Sarpeshkar, Rahul and Lyon, Richard F. and Mead, Carver (1998) A Low-Power Wide-Dynamic-Range Analog VLSI Cochlea. In: Neuromorphic Systems Engineering : Neural Networks in Silicon. Springer International Series in Engineering and Computer Science. No.447. Kluwer Academic , Boston, MA, pp. 49-103. ISBN 0792381580. https://resolver.caltech.edu/CaltechAUTHORS:20150112-105156628

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Abstract

In this paper we describe a cochlea that attains a dynamic range of 6ldB at the BF of a typical cochlear stage by using four techniques: 1. The previously described WLR 2. A low-noise second-order filter topology 3. Dynamic gain control (AGC) 4. The architecture of overlapping cochlear cascades In addition, we use three techniques that ensure the presence of a robust infrastructure in the cochlea: l. Automatic offset-compensation circuitry in each cochlear filter prevents offset accumulation along the cochlea. 2. Cascode circuitry in the WLRs increase the latter's DC gain, and prevent low-frequency signal attenuation in the cochlea. 3. Translinear bipolar biasing circuits provide Qs that are approximately invariant with corner frequency, and allow better matching. Bipolar biasing circuits were first used in cochlear designs by [32]. We shall discuss all of these preceding techniques in this paper.


Item Type:Book Section
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http://www.springer.com/engineering/circuits+%26+systems/book/978-0-7923-8158-7PublisherBook
Additional Information:© 1998 Kluwer Academic
Series Name:Springer International Series in Engineering and Computer Science
Issue or Number:447
Record Number:CaltechAUTHORS:20150112-105156628
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:20150112-105156628
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:53566
Collection:CaltechAUTHORS
Deposited By: Kristin Buxton
Deposited On:13 Jan 2015 02:13
Last Modified:03 Oct 2019 07:50

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