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Asynchronous techniques for system-on-chip design

Martin, Alain J. and Nyström, Mika (2006) Asynchronous techniques for system-on-chip design. Proceedings of the IEEE, 94 (6). pp. 1089-1120. ISSN 0018-9219. https://resolver.caltech.edu/CaltechAUTHORS:MARprocieee06

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Abstract

SoC design will require asynchronous techniques as the large parameter variations across the chip will make it impossible to control delays in clock networks and other global signals efficiently. Initially, SoCs will be globally asynchronous and locally synchronous (GALS). But the complexity of the numerous asynchronous/synchronous interfaces required in a GALS will eventually lead to entirely asynchronous solutions. This paper introduces the main design principles, methods, and building blocks for asynchronous VLSI systems, with an emphasis on communication and synchronization. Asynchronous circuits with the only delay assumption of isochronic forks are called quasi-delay-insensitive (QDI). QDI is used in the paper as the basis for asynchronous logic. The paper discusses asynchronous handshake protocols for communication and the notion of validity/neutrality tests, and completion tree. Basic building blocks for sequencing, storage, function evaluation, and buses are described, and two alternative methods for the implementation of an arbitrary computation are explained. Issues of arbitration, and synchronization play an important role in complex distributed systems and especially in GALS. The two main asynchronous/synchronous interfaces needed in GALS-one based on synchronizer, the other on stoppable clock-are described and analyzed.


Item Type:Article
Related URLs:
URLURL TypeDescription
https://doi.org/10.1109/JPROC.2006.875789DOIUNSPECIFIED
Additional Information:© Copyright 2006 IEEE. Reprinted with permission. Manuscript received September 14, 2005; revised March 3, 2006. [Posted online: 2006-07-10] This work was supported in part by the Defense Advanced Research Projects Agency (DARPA). The authors would like to thank J. Dama, W. Jang, M. Josephs, J.L. Martin, M. Naderi, K. Papadantonakis, and P. Prakash for their excellent comments on the paper.
Subject Keywords:Arbiter; asynchronous; asynchronous bus; asynchronous/synchronous interface; C-element; completion tree; dual-rail; globally asynchronous and locally synchronous (GALS); half-buffer; handshake protocol; isochronic fork; metastability; passive–active buffer; precharge half-buffer (PCHB); quasi-delay-insensitive (QDI); stoppable clock; synchronizer
Issue or Number:6
Record Number:CaltechAUTHORS:MARprocieee06
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:MARprocieee06
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:5363
Collection:CaltechAUTHORS
Deposited By: Archive Administrator
Deposited On:13 Oct 2006
Last Modified:02 Oct 2019 23:22

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